UC Riverside study moves HBM4 memory controller functions onto the base die

Where should memory control live?

Two researchers at the University of California, Riverside, Tharunya Yogananda and Wantong Li, have released a study examining where the functions of a high bandwidth memory controller should physically sit. Semiconductor Engineering reported the publication on 13 November 2026. The work appears as arXiv paper 2611.10930.

The question matters because HBM4, the newest generation of high bandwidth memory used beside AI processors, changes a long-standing assumption. Earlier memory stacks kept their base die simple, but HBM4 allows that base die to be built on a logic process. That means more sophisticated control circuitry can sit directly under the DRAM, close to the memory cells rather than inside the host processor.

How the study was organised

The paper is described as the first systematic, quantitative examination of placing individual controller functions between two locations: the host chip and the HBM4 base die, which sits on a silicon interposer. The authors split the memory controller into its main jobs, such as maintenance tasks and request scheduling.

They then evaluated four arrangements. At one extreme, the entire controller runs on the host. At the other, everything moves onto the base die. Between those sit hybrid designs, in which either maintenance or scheduling functions are shifted to the memory stack while the rest stays on the host.

Why it matters for AI hardware

High bandwidth memory is the stacked DRAM that feeds data to AI accelerators, and its bandwidth requirements keep growing. Moving control logic closer to the memory can reduce the distance signals travel, but it also raises questions about heat, cost and how much logic a memory vendor should build into a product.

Because HBM4 opens the door to logic-capable base dies, memory makers and processor designers now face a genuine design choice rather than a fixed architecture. Studies like this one give the industry a framework for deciding which functions benefit from relocation and which are better left with the host.

What is known and what is not

The findings summarised here come from the abstract excerpt published by Semiconductor Engineering. The full paper, including its measured results on performance, power and area, is available on arXiv for readers who want the detailed data.

The research is academic work and does not reflect any announced product. Whether memory vendors or accelerator designers adopt partitioned controller designs in commercial HBM4 parts remains to be seen.